Serializer/Deserializer (SerDes) links are widely used in various high-speed communications applications. The links generally provide for converting parallel data into serial form for high-speed data transfers across a minimum number of electrical paths. FIG. 1 illustrates several applications for SerDes links, such as board-to-board links 102, chip-to-chip links 104, backplane links 106, and box-to-box links 108, to name a few.
One particular form of SerDes link involves a dual-duplex architecture, shown generally in FIG. 2, that employs dual links 202 and 204 that both operate to transmit and receive data bidirectionally. While this architecture works well for its intended applications, in some situations, a transmit data rate may be different than a receive data rate for the same link. What is needed is a power-efficient method and apparatus to support asymmetric operations for dual-duplex SerDes links.